1. Field of the Invention
The present invention relates to a current detection circuit that detects a read current from a memory cell in a memory system such as a ROM (read only memory) or the like.
2. Description of the Related Art
FIG. 1 shows an example of a conventional current detection circuit in a ROM which is disclosed in Japanese Patent Kokai No. S61-129800 (Patent Literature 1) as a read circuit. This conventional current detection circuit includes PMOS transistors (P channel type MOS Field Effect Transistors) 1, 2 of the same shape, NMOS transistors (N channel type MOS Field Effect Transistors) 3, 4 of the same shape, and NMOS transistors 5, 6 of the same shape. As shown in FIG. 1, the PMOS transistor 1 and the NMOS transistors 3 and 5 are series connected by the connection at the drain and the source of each transistor. The source of the PMOS transistor 1 constituting an end of the series circuit is connected to an application terminal of a voltage Vcc and the source of the NMOS transistor 5 constituting the other end of the series circuit is connected to an application terminal of a ground potential Vss=0V. The gates of the PMOS transistor 1 and the NMOS transistors 3 and 5 are commonly connected, and further connected to a node N1 which is a junction point of the drain of the PMOS transistor 1 and the drain of the NMOS transistor 3. Similarly, the PMOS transistor 2 and the NMOS transistors 4 and 6 are series connected at the drain and the source of each transistor. The source of the PMOS transistor 2 constituting an end of the series circuit is connected to the application terminal of the voltage Vcc and the source of the NMOS transistor 6 constituting the other end of the series circuit is connected to the application terminal of a ground potential Vss. The gates of the PMOS transistor 2 and the NMOS transistor 4 are connected to a connection line of the above-described node N1, and the gate of the NMOS transistor 6 is connected to a node N2 which is a junction point of the drain of the PMOS transistor 2 and the drain of the NMOS transistor 4.
A reference current Ir is supplied to a node N3 which is a junction point of the source of the NMOS transistor 3 and the drain of the NMOS transistor 5. Furthermore, one of a plurality of data lines to which a plurality of memory cells (not shown) constituting a memory matrix are connected is selectively connected to a node N4 which is a junction point of the source of the NMOS transistor 4 and the drain of the NMOS transistor 6. On of the plurality of data lines is selected by a data line decoder (not shown), and a detection current I from a memory cell is supplied to the node N4 via the selected one of the data lines. Details of the memory cell, the data line decoder and the word line decoder which will be described later are disclosed in the Patent Literature 1.
The above described node N1 and node N2 are connected to an output terminal via a differential amplifier 9.
In the conventional current detection circuit described above, when reading recorded data of a certain memory cell in the memory matrix in the form of a current, the memory cell is selected by the above-described data line decoder and a word line decoder which is not depicted, and the selected memory cell is connected to the node N4 via the data line. The detection current I flows into the node N4 from the selected memory cell and a reference current Ir for the detection current I flows into the node N3. By these flows of currents, a difference voltage indicating the magnitude relationship between the reference current Ir and the detection current I appears between the node N1 and the node N2, and the difference voltage is amplified by the differential amplifier 9 and outputted as read data of the selected memory cell. In this process, the potential at the node N4 is fixed at a potential determined according to the circuit constants and the amount of the reference current Ir, and a potential variation by the electric charge stored in a stray capacity of the data line caused by the switching of the data line is rapidly compensated, so that speedup of the access time is realized.